Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor
نویسندگان
چکیده
This paper describes a tool called Focus that is currently being used for the timing ver$cation and sizing of domino CMOS circuits in a Power PCTM microprocessor Domino CMOS circuits introduce more complex timing and sizing requirements compared to conventional static circuits. This paper shows how these requirements are addressed in Focus. Some case studies involving the application of Focus on production circuits are also described
منابع مشابه
Timing Optimization of Mixed Static and Domino Logic
A timing optimization algorithm dealing with circuits containing mixed domino and static logic is described. Transistor-level node timing constraints of domino logic is described. The optimization procedure preserves the requirements of maintaining adequate noise margins by constraining the sizing procedure. After sizing, charge-sharing problems are identi ed with a new method and recti ed.
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